Syllabus

1.1. Introduction LINUX-Based Scripting Language
1.2. Digital Circuit Design and Verification using Verilog/System-Verilog
1.3. Advanced Verilog constructs for Design and Verification
1.4. Functional Verification
1.5. Design Constraints
1.6. Gated-Logic and DFT
1.7. Logic Synthesis and Gate-Level Simulation
1.8. Physical Layout, DRC, ERC and LVS
1.9. Static Timing Analysis (STA)
1.10. LEC and Verification
1.11. GDSII for Tape-Out